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KS57C21632/P21632
PRODUCT OVERVIEW
1
OVERVIEW
PRODUCT OVERVIEW
The KS57C21632 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With an up-to-896-dot LCD direct drive capability, and flexible 8-bit timer/counters, the KS57C21632 offers an excellent design solution for a high-end LCD game. Up to 12 pins of the 100-pin QFP package can be dedicated to I/O. Seven vectored interrupts provide fast response to internal and external events. In addition, the KS57C21632's advanced CMOS technology provides for low power consumption.
OTP
The KS57C21632 microcontroller is also available in OTP (One Time Programmable) version, KS57P21632. KS57P21632 microcontroller has an on-chip 32 K-byte one-time-programmable EPROM instead of masked ROM. The KS57P21632 is comparable to KS57C21632, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
KS57C21632/P21632
FEATURES
Memory * * 768 x 4-bit RAM (excluding LCD display RAM) 32,768 x 8-bit ROM Interrupts * * * 12 I/O Pins * I/O: 12 pins Memory-Mapped I/O Structure * LCD Controller/Driver * * * * 56 segments and 16 common terminals (8, 12 and 16 common selectable) Capacitor bias for LCD output. Voltage booster and regulator All dots can be switched on/off Oscillation Sources 8-bit Basic Timer * * 4 interval timer functions Watch-dog timer * * * * One 16-bit Timer/Counter 1 * * * * Programmable 16-bit timer Arbitrary clock output (TCLO1) Inverted clock output (TCLO1) Configurable two 8-bit timer/counters Instruction Execution Times * * 0.95, 1.91, 15.3 s at 4.19 MHz (main) 122 s at 32.768 kHz (subsystem) * Crystal, ceramic, or RC for main system clock Crystal oscillator for subsystem clock Main system clock frequency: 0.4-4.19 MHz Subsystem clock frequency: 32.768 kHz CPU clock divider circuit (by 4, 8, or 64) Power-Down Modes * * * Idle mode (only CPU clock stops) Stop mode (main system oscillation stops) Subsystem clock stop mode Data memory bank 15 Three Internal vectored interrupt Four external vectored interrupts Two quasi-interrupts
Watch Timer * * * Time interval generation: 0.5 s, 3.9 ms at 32768 Hz Four frequency outputs to BUZ pin and BUZ pin Clock source generation for LCD
Operating Temperature * - 40 C to 85 C
Operating Voltage Range * 2.2 V to 3.4 V (0.4 MHz to 4.19 MHz)
Battery Level Detector * * Programmable low voltage detector One criteria voltage (2.4 V)
Package Type * 100-pin QFP or pellet
1-2
KS57C21632/P21632
PRODUCT OVERVIEW
BLOCK DIAGRAM
RESET
XIN XOUT XTIN XTOUT
Basic (Watchdog) Timer
P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P0.3/BUZ/K3 P0.2/BUZ/K2 P0.1/TCLO1/K1 P0.0/TCLO1/K0 P2.0/CLO P2.1/TCL1 P2.2 P2.3
I/O Port 1
Interrupt Control Block
Clock
Instruction Register
Watch Timer
I/O Port 0
Internal Interrupts
Program Counter
Voltage Regulator/ Booster
TEST 2 CA CB
I/O Port 2
Instruction Decoder
Program Status Word
LCD Driver/ Controller
SEG0-SEG55 COM0-COM15 VLC1-VLC5
8-bit Timer Counter 1A 8-bit Timer Counter 1B
16-bit Timer Counter 1
Arithmetic and Logic Unit
Stack Pointer
Battery Level Detector
768 x 4-bit Data Memory
32-Kbyte Program Memory
Figure 1-1. KS57C21632 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
KS57C21632/P21632
PIN ASSIGNMENTS
SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VLC1 VLC2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG18 SEG19 SEG21 SEG22 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47
VLC3 VLC4 VLC5 CA CB TEST2 P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 BUZ/P0.3/K3
BUZ/P0.2/K2 TCLO1/P0.1/K1
TCLO1/P0.0/K0 VDD VSS XOUT XIN TEST1 XTIN XTOUT
RESET
CLO/P2.0 TCL1/P2.1 P2.2 P2.3 COM15 COM14 COM13 COM12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
KS57C21632
Figure 1-2. KS57C21632 100-QFP Pin Assignment Diagram
100-QFP 1420 C
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11
1-4
KS57C21632/P21632
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. KS57C21632 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P0.3 Pin Type I/O Description 4-bit I/O port. 1-bit and 4-bit read/write and test are possible. Individual pins are software configurable as input or output. Individual pins are software configurable as opendrain or push-pull output. Individual pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. Same as port 0 Number 14 13 12 11 Share Pin TCLO1/K0 TCLO1/K1 BUZ/K2 BUZ/K3
P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 INT0, INT1 INT2 INT4 BUZ BUZ CLO TCL1 TCLO1 TCLO1 COM0-COM15 SEG0-SEG55
I/O
10 9 8 7 23 24 25 26 10, 9 8 7 11 12 23 24 13 14 42-27 98-43
INT0 INT1 INT2 INT4 CLO TCL1
I/O
Same as port 0
I/O I/O I/O I/O I/O I/O I/O I/O I/O O O
External interrupts. The triggering edge for INT0 and INT1 is selectable. Quasi-interrupt with detection of rising or falling edges. External interrupt with detection of rising and falling edges. 2 kHz, 4 kHz, 8 kHz or 16 kHz frequency output for buzzer signal. Inverted BUZ signal Clock output External clock input for timer/counter 1 Timer/counter 1 inverted clock output Timer/counter 1 clock output LCD common signal output LCD segment signal output
P1.0, P1.1 P1.2 P1.3 P0.3/K3 P0.2/K2 P2.0 P2.1 P0.1/K1 P0.0/K0 - -
1-5
PRODUCT OVERVIEW
KS57C21632/P21632
Table 1-1. KS57C21632 Pin Descriptions (Continued) Pin Name K0-K3 VDD VSS RESET CA, CB VCL1-VCL2 VCL3-VCL5 TEST2 XIN, XOUT XTIN, XTOUT TEST1 Pin Type I/O - - I - - I - - I Main power supply Ground Reset signal Capacitor terminal for voltage boosting LCD power supply Test input (must be connected VSS) Crystal, ceramic or RC oscillator pins for system clock Crystal oscillator pins for subsystem clock Test input (must be connected to VSS) (2) Description External interrupt (triggering edge is selectable) Number 14-11 15 16 22 4, 5 99-100 1-3 6 18, 17 20, 21 19 Share Pin P0.0-P0.3 - - - - - - - - -
NOTES 1. Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode. 2. Refer to chapter 16 for OTP version.
Table 1-2. Overview of KS57C21632 Pin Data Pin Name P0.0-P0.3 P1.0-P1.3 P2.0-P2.1 P2.2-P2.3 COM0-COM15 SEG0-SEG55 VDD VSS RESET CA CB VLC1-VLC5 XIN, XOUT XTIN, XTOUT TEST1, 2 Share Pins TCLO1/K0, TCLO1/K1 BUZ/K2, BUZ/K3 INT0, INT1, INT2, INT4 CLO, TCL1 - - - - - - - - - - - - I/O Type I/O I/O I/O I/O O O - - I - - - - - I Reset Value Input Input Input Input Low Low - - - - - - - - - Circuit Type E-2 E-2 E-2 E-2 H-6 H-6 - - B - - - - - -
1-6
KS57C21632/P21632
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD PNE VDD Resistor Enable I/O Pull-up Resistor
VDD
P-Channel In N-Channel
Data
Output Disable
Schmitt Trigger
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type E-2
VLC1
VLC2 VDD VLC3/VLC4 Pull-up Resistor SEG/COM Data IN Schmitt Trigger VLC3/VLC4 Out
VLC5
VSS
Figure 1-4. Pin Circuit Type B
Figure 1-6. Pin Circuit Type H-6
1-7
PRODUCT OVERVIEW
KS57C21632/P21632
NOTES
1-8
KS57C21632/P21632
ELECTRICAL DATA
14
OVERVIEW
ELECTRICAL DATA
In this section, information on KS57C21632 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics -- Absolute maximum ratings -- D.C. electrical characteristics -- Main system clock oscillator characteristics -- Subsystem clock oscillator characteristics -- I/O capacitance -- Battery level detector characteristics -- Voltage booster characteristics -- A.C. electrical characteristics -- Operating voltage range Stop Mode Characteristics and Timing Waveforms -- RAM data retention supply voltage in stop mode -- Stop mode release timing when initiated by RESET -- Stop mode release timing when initiated by an interrupt request Miscellaneous Timing Waveforms -- A.C timing measurement point -- Clock timing measurement at XIN -- Clock timing measurement at XTIN -- Input timing for RESET signal -- Input timing for external interrupts and quasi-interrupts
14-1
ELECTRICAL DATA
KS57C21632/P21632
Table 14-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI VO I OH I OL Ports 0-2 - One I/O pin active All I/O pins active Output Current Low One I/O pin active Conditions - Rating - 0.3 to + 4.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 30 + 30 (Peak value) + 15 (note) Total for pins 0, 1 TA Tstg + 100 (Peak value) + 60 (note) Operating Temperature Storage Temperature - -
Duty . C C
Units V V V mA
mA
- 40 to + 85 - 65 to + 150
NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value x
Table 14-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.2 V to 3.4 V) Parameter Input High Voltage Symbol VIH1 VIH2 Input Low Voltage VIL1 VIL2 Output High Voltage Output Low Voltage VOH Conditions Ports 0, 1, 2, and RESET XIN, XOUT, and XTIN Ports 0, 1, 2, and RESET XIN, XOUT, and XTIN VDD = 2.2 V to 3.4 V IOH = - 1 mA Ports 0, 1, 2 VDD = 2.2 V to 3.4 V IOL = 5 mA Ports 0, 1, 2 VDD - 1.0 - Min 0.8 VDD VDD - 0.1 - - Typ - Max VDD VDD 0.2 VDD 0.1 - V V Units V
VOL
-
-
1.0
V
14-2
KS57C21632/P21632
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.2 V to 3.4 V) Parameter Input High Leakage Current Symbol ILIH1 Conditions VI = VDD All input pins except those specified below for ILIH2 VI = VDD RESET, XIN, XOUT, XTIN and XTOUT VI = 0 V All input pins except RESET, XIN, XOUT, XTIN and XTOUT VI = 0 V XIN, XOUT, XTIN and XTOUT VO = VDD All output pins VO = 0 V All output pins VI = 0 V; VDD = 3 V, Ports 0-2 VI = 0 V; VDD = 3 V, RESET VLCD = 5.0 V - 15 A per common pin VLCD = 5.0 V - 15 A per common pin - - 50 200 - - - 100 450 - - - Min - Typ - Max 3 Units A
ILIH2 Input Low Leakage Current ILIL1
20 -3 A
ILIL2 Output High Leakage Current Output Low Leakage Current Pull-up Resistor ILOH ILOL RL1 RL2 |VLCD-COMi| Voltage Drop (i = 0-15) |VLCD-SEGx| Voltage Drop (i = 0-55) VDC
- 20 3 -3 200 800 120 mV A A k
VDS
-
-
120
14-3
ELECTRICAL DATA
KS57C21632/P21632
Table 14-2. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 2.2 V to 3.4 V) Parameter Supply Current (1) Symbol IDD1 Conditions VDD = 3 V 10% crystal oscillator C1 = C2 = 22 pF Idle mode; VDD = 3 V 10% crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10% 32 kHz crystal oscillator Idle mode; VDD = 3 V 10% 32 kHz crystal oscillator (LCD off) Stop mode; VDD = 3 V 10% SCMOD = 0000B, XTIN = 0 V Stop mode; VDD = 3 V 10% SCMOD = 0000B 4.19 MHz (PCON = 3H) 4.19 MHz (PCON = 3H) Min - Typ 1.2 Max 3 Units mA
IDD2
-
0.4
1
mA
IDD3 (2) IDD4 (2) IDD5
- - -
15 6 0.5
30 15 3
A A A
0.2
2
NOTES: 1. Data includes power consumption for subsystem clock oscillation. 2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the subsystem clock is used. 3. Current in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage booster circuit, and port drive currents.
output
14-4
KS57C21632/P21632
ELECTRICAL DATA
Table 14-3. Main System Clock Oscillator Characteristics (TA = - 40 C to + 85 C, VDD = 2.2 V to 3.4 V) Oscillator Ceramic Oscillator Clock Configuration
XIN XOUT
Parameter Oscillation frequency (1)
Test Condition -
Min 0.4
Typ -
Max 4.19
Units MHz
C1
C2
Stabilization time (2)
Stabilization occurs when VDD is equal to the minimum oscillator voltage range; VDD = 3 V -
-
-
4
ms
Crystal Oscillator
XIN
XOUT
Oscillation frequency (1)
0.4
-
4.19
MHz
C1
C2
Stabilization time (2) External Clock
XIN XOUT
VDD = 3 V -
- 0.4
- -
10 4.19
ms MHz
XIN input frequency (1)
XIN input high and low level width (tXH, tXL) RC Oscillator
XIN R XOUT
- VDD = 3 V
83.3 0.4
- -
1250 2
ns MHz
Frequency
NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is terminated.
14-5
ELECTRICAL DATA
KS57C21632/P21632
Table 14-4. Recommended Oscillator Constants (TA = - 40 C + 85 C, VDD = 2.2 V to 3.4 V) Manufacturer Series Number (1) Frequency Range Load Cap (pF) C1 TDK FCR FCR CCR M5 MC5 MC3 3.58 MHz-6.0 MHz 3.58 MHz-6.0 MHz 3.58 MHz-6.0 MHz 33
(2)
Oscillator Voltage Range (V) MIN 2.2 2.2 2.2 MAX 3.4 3.4 3.4
Remarks
C2 33
(2)
Leaded Type On-chip C Leaded Type On-chip C SMD Type
(3)
(3)
NOTES: 1. Please specify normal oscillator frequency. 2. On-chip C: 30pF built in. 3. On-chip C: 38pF built in.
Table 14-5. Subsystem Clock Oscillator Characteristics (TA = - 40 C to + 85 C, VDD = 2.2 V to 3.4 V) Oscillator Crystal Oscillator Clock Configuration
XTIN XTOUT
Parameter Oscillation frequency (1)
Test Condition -
Min 32
Typ 32.768
Max 35
Units kHz
C1
C2
Stabilization time (2) External Clock
XT IN XT OUT
VDD = 3.0 V
(1)
- 32
1.0 -
3 100
s kHz
XTIN input frequency
-
XTIN input high and low level width (tXTL, tXTH)
-
5
-
15
s
NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
14-6
KS57C21632/P21632
ELECTRICAL DATA
Table 14-6. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - - - Typ - - - Max 15 15 15 Units pF pF pF
Table 14-7. Battery Level Detector Characteristics (TA = - 40 C to + 85 C, VDD = 2.2 V to 3.4 V) Parameter BLD Voltage BLD Circuit Response Time BLD Operating Current Symbol VB0 TB IBL Condition BLC = 0 (when BREF = #05H) fw = 32.768 kHz - Min 2.2 - - Typ 2.4 - - Max 2.6 1 10 Units V ms A
14-7
ELECTRICAL DATA
KS57C21632/P21632
Table 14-8. Voltage Booster Characteristics (TA = - 40 C to + 85 C, VDD = 2.2 V to 3.4 V, C1 = C2 = C3 = C4 = 0.1 F, CA/CB = 0.1 F) Parameter Liquid Crystal Drive Voltage (1) Symbol VLC5 Conditions Connect a 1 M load resistance between VSS and VLC5 (2) (no panel load) LCR = 0 Min Typ x 0.9 Typ 0.85 Max Typ x 1.1 Units V
LCR = 1 LCR = 2 LCR = 3 LCR = 4 LCR = 5 LCR = 6 LCR = 7 VLC4/3 VLC2 VLC1 Voltage Regulator & Booster Consumed Current IVB Connect a 1 M load resistance between 2 x VLC5 VSS and VLC4/3 (2) (no panel load) x 0.9 Connect a 1 M load resistance between 3 x VLC5 VSS and VLC2 (2) (no panel load) x 0.9 Connect a 1 M load resistance between 4 x VLC5 VSS and VLC1 (2) (no panel load) x 0.9 VDD = 3 V LCR = 7 Display on (LCON = 3H) -
0.90 0.95 1.00 1.05 1.10 1.15 1.20 - - - 5.0 2 x VLC5 x 1.1 3 x VLC5 x 1.1 4 x VLC5 x 1.1 10 A
NOTES: 1. The operating voltage of booster ranges from 2.4 V to 3.4 V. 2. The 1 M load resistance is connected only to selected symbol (VLC1-VLC5) conditions to measure the properties of the circuit.
Table 14-9. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.2 V to 3.4 V) Parameter Instruction Cycle Time (note) Interrupt Input High, Low Width
RESET Input Low
Symbol tCY
Conditions VDD = 2.2 V to 3.4 V With subsystem clock (fxt)
Min 0.95 114 10 10
Typ - 122 - -
Max 64 125 - -
Units s
fINTH, fINTL tRSL
INT0-INT2, INT4 K0-K3, TLC1 Input
s s
Width
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
14-8
KS57C21632/P21632
ELECTRICAL DATA
CPU Clock 1.05 MHz
Main Oscillator Frequency (Divided by 4) 4.2 MHz
15.6 kHz 1 2 2.2 3 3.4 4 5 6 7
Supply Voltage (V) CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 14-1. Standard Operating Voltage Range
Table 14-10. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions - VDDDR = 2.2 V - Released by RESET Released by interrupt Min 2.2 - 0 - - Typ - 0.1 - 217/fx
(2)
Max 3.4 10 - - -
Unit V A s ms
NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
14-9
ELECTRICAL DATA
KS57C21632/P21632
TIMING WAVEFORMS
Internal RESET Operation Stop Mode Data Retention Mode Idle Mode Normal Mode
~ ~ ~ ~
VDD
VDDDR Execution of STOP Instrction
RESET
tWAIT tSREL
Figure 14-2. Stop Mode Release Timing When Initiated by RESET
Idle Mode
~ ~ ~ ~
Stop Mode Data Retention Mode
Normal Mode
VDD
VDDDR Execution of STOP Instrction
tSREL
tWAIT Power-down Mode Terminating Signal (Interrupt Request)
Figure 14-3. Stop Mode Release Timing When Initiated by Interrupt Request
14-10
KS57C21632/P21632
ELECTRICAL DATA
0.8 VDD Measurement Points 0.2 VDD
0.8 VDD
0.2 VDD
Figure 14-4. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/fx tXL tXH
XIN
VDD - 0.1 V 0.1 V
Figure 14-5. Clock Timing Measurement at XIN
1/fxt tXTL tXTH
XTIN
VDD - 0.1 V 0.1 V
Figure 14-6. Clock Timing Measurement at XTIN
14-11
ELECTRICAL DATA
KS57C21632/P21632
tRSL
RESET
0.2 VDD
Figure 14-7. Input Timing for RESET Signal
tINTL
tINTH
INT0, 1, 2, 4, K0 to K3 TCL1
0.8 VDD 0.2 VDD
Figure 14-8. Input Timing for External Interrupts
14-12
KS57C21632/P21632
MECHANICAL DATA
15
OVERVIEW
MECHANICAL DATA
This section contains the following information about the device package: -- Package dimensions in millimeters
15-1
MECHANICAL DATA
KS57C21632/P21632
23.90 20.00 0-8 0.15
+ 0.10 - 0.05
17.90
14.00
100-QFP-1420C
0.10 MAX
#1 0.65
0.30
+ 0.10 - 0.05
0.15 MAX
0.05 MIN (0.58) 2.65 3.00 MAX
0.80
NOTE: Dimensions are in millimeters.
Figure 15-1. 100-QFP-1420C Package Dimensions
15-2
0.80
#100
KS57C21632/P21632
KS57P21632 OTP
16
OVERVIEW
KS57P21632 OTP
The KS57P21632 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the KS57C21632 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The KS57P21632 is fully compatible with the KS57C21632, both in function and in pin configuration. Because of its simple programming requirements, the KS57P21632 is ideal for use as an evaluation chip for the KS57C21632.
16-1
KS57P21632 OTP
KS57C21632/P21632
SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VLC1 VLC2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG18 SEG19 SEG21 SEG22 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47
VLC3 VLC4 VLC5 CA CB TEST2 P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 BUZ/P0.3/K3 BUZ/P0.2/K2 SDAT /TCLO1/P0.1/K1 SCLK /TCLO1/P0.0/K0 VDD/VDD VSS/VSS XOUT XIN VPP/TEST1 XTIN XTOUT RESET /RESET CLO/P2.0 TCL1/P2.1 P2.2 P2.3 COM15 COM14 COM13 COM12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
KS57P21632
Figure 16-1. KS57P21632 Pin Assignments (100-QFP Package)
100-QFP 1420 C
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11
16-2
KS57C21632/P21632
KS57P21632 OTP
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P0.1 Pin Name SDAT Pin No. 13 During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/pushpull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip initialization Logic power supply pin. VDD should be tied to +5 V during programming.
P0.0 TEST
SCLK VPP (TEST1)
14 19
I/O I
RESET
RESET
22 15/16
I I
VDD/VSS
VDD/VSS
Table 16-2. Comparison of KS57P21632 and KS57C21632 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability 2.2 V to 3.4 V VDD = 5 V, VPP (TEST1) = 12.5 V 100 QFP User Program 1 time 100 QFP Programmed at the factory KS57P21632 32 Kbyte EPROM KS57C21632 32 Kbyte mask ROM 2.2 V to 3.4 V -
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST1) pin of the KS57P21632, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16-3 below. Table 16-3. Operating Mode Selection Criteria VDD 5V VPP (TEST1) 5V 12.5 V 12.5 V 12.5 V REG/MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection Mode
NOTE: "0" means Low level; "1" means High level.
16-3
KS57P21632 OTP
KS57C21632/P21632
Table 16-4. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.2 V to 3.4 V) Parameter Supply Current (1) Symbol IDD1 Conditions VDD = 3 V 10% 4.19 MHz (PCON = 3H) crystal oscillator C1 = C2 = 22 pF Idle mode; VDD = 3 V 10% 4.19 MHz (PCON = 3H) crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10% 32 kHz crystal oscillator Idle mode; VDD = 3 V 10% 32 kHz crystal oscillator Stop mode; VDD = 3 V 10% Stop mode; VDD = 3 V 10% SCMOD = 0000B, XTIN = 0 V SCMOD = 0100B - Min - Typ 1.2 Max 3.0 Units mA
IDD2
0.4
1.0
IDD3 (2) IDD4 (2) IDD5
15 6 0.5 0.2
30 1.5 3 2
A
NOTES: 1. Data includes power consumption for subsystem clock oscillation. 2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the subsystem clock is used. 3. Current in the following circuits are not included; on-chip pull-up resistors, voltage boosting capacitors, and output port drive currents.
16-4
KS57C21632/P21632
KS57P21632 OTP
CPU Clock 1.05 MHz
Main Oscillator Frequency (Divided by 4) 4.2 MHz
15.6 kHz 1 2 2.2 3 3.4 4 5 6 7
Supply Voltage (V) CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 16-2. Standard Operating Voltage Range
16-5

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